A semiconductor device such as an integrated circuit chip is produced by a sequence of hundreds of process steps. Many such process steps require a lithographic mask through which a pattern is imprinted on a photoresist layer. The design of lithographic masks nowadays involves the prediction of the printed pattern taking into account optical, resist and etch phenomena, which occur at the scale of the mask features and below. These effects cause unavoidable deviations on the printed pattern with respect to the design intent. So-called ‘Electronic Design Automation’ (EDA) tools, such as ‘Optical Proximity Correction’ (OPC) software is used for determining and making corrections to the intended initial mask design to give the best possible approximation of the design intent on the printed wafer. OPC optimization is based on the fragmentation of the initial design edges to compensate for the given phenomena, and relies on an accurate modelling to predict simulated contours of the printed features. In some embodiments, the OPC-based tools may provide a simulated ‘process window’ (PW) of many features. A PW defines the printability performance limits in terms of the focus and dose settings of a lithographic printing tool, within which limits a reliable print of the pattern is obtainable. Some patterns can have bigger PW than other patterns, due to various reasons such as design geometry, accuracy of the OPC modelling, and more.
Primarily for the features showing the smallest PW, the simulated PW are subsequently verified experimentally by manufacturing the mask and using it to print the pattern on a plurality of die areas of a photosensitive resist layer. Each die area is being printed with varying values of the focus and dose conditions. The experimental PW are determined by measuring features on the plurality of die areas. Differences between the experimental and simulated PW are evaluated and may necessitate further OPC-based optimization of the mask design.
Different measurement techniques are known for analyzing the printed dies. CD-SEM (Critical Dimension-Scanning Electron Microscope) is used to measure the Critical Dimension (CD) of a number of pattern features on the printed dies. Because of the characteristics of the measurement technique, only specific feature types can be measured, such as regular line/space widths and distances between opposite line-ends. This means that the features that are most critical, according to the OPC model, and presenting the most complex geometry can often not be measured. This is particularly true considering logic structures, which have complex 2D geometries and are not regularly distributed. The PW obtained in this way does not necessarily analyze the most likely positions to fail (near corners, specific line-ends, etc.).
Verification of printed patterns on the basis of extracted contours is also known as such, as illustrated for example in WO2014208202. As will be explained in more detail on the basis of a specific example, many parameters obtained from contours do not accurately reflect specific shapes of the printed features. Also, when such contour-based parameters are determined as a function of focus and dose, it is often seen that when fitting the values with a best fitting polynomial, the measured values deviate from the best fitting polynomial in an important way. These drawbacks make it difficult to obtain a reliable Process Window estimation.
As the dimensions of printed features decrease with the evolution towards sub 32 nm nodes in semiconductor processing, the criticality of the above-described design and inspection processes becomes ever greater.